James Edward Vigil (US Born, US Citizen: Last Clearance 1984-1986 SECRET)
RESUME Rev 2020.0.2 Southwest/Central Florida, California and mid-Atlantic coast
Cellular/Voicemail 239-398-8691
Email: [email protected]

DESIRED POSITION: FPGA Designer. Background includes Analog Front End Component Selection, LabTest Prototype C/Assembly Code on Test Hardware For Fixed/FloatingPt DSPs, Embedded Systems, Systems Integration, SW Test Development (R&D Lab Equip’t), Wireless Signals/Protocols, FixedPt/FloatingPt Verilog or VHDL Digital Signal Processing, DDR3/4 Memory/Data Flow, SW Defined Radio, Satellite Comms, RF Baseband Digital Design HW Development and RF Debug. Xilinx Zynq Ultrascale+ Hi-Speed SerDes(Gigabit GTH Transceiver) in MPSOC. FPGA Designs for Space HW Testing.

CAREER SUMMARY
Designed 22+FPGAs(2 FPGAs DO254 Aerospace, including 3 MIL-STD Aerospace) and 14ASIC(5 Mixed Signal)/SOC's in teams and as individual lead, with 9yrs Static Timing, 1yr ASIC Physical Design, 10yrs VHDL, 8yrs Verilog, 1yr System Verilog and 12yrs Digital/Moderate Analog/RF PCB schematics on Mentor, Cadence, IBM, Synopsys, MATLAB and MATHCAD tools). FPGA, ASICs implemented DSP(Digital Signal Processing) Filters, PSK(DPSK, BPSK, QPSK)signaling, (Convolutional, Walsh, Turbo, CDMA, ODFM-like, MFM) modulation codes, (CRC, RS Block, Hamming ECC) error detect/correction codes, Analog Buffers, Amplifiers, Filters, MIL-STD IFF RF baseband and Video Framing, interfaces to UART, SPI, CAN Bus, VME32/64, PCI, PCIx, MIL-STD-1553, Arinc 429, RS422/485, IBM PowerPC Address, Data Buses. Embedded Microcontroller systems Lab HW/SW debug of multiple product SOCs/DSPs. 4yrs Safety Design: 1yrs Aerospace + 3yrs Medical. 10+yrs Schematics. Close interaction with internal engineering team and external customers.

• FPGA Designs implemented Digital Signal Processing (DSP) algorithms to realize customer hardware design requirements, using industry standard tool sets:

                  - Pipeline time+frequency data, processed by FFT/IFFT, FIR's and IIR's for Real-time DSP algorithms. 
                  - Hardware integration in lab environment, with lab tests matched to comprehensive verification simulations.
                  - Familiar with hi-speed circuit design: work with PCB designers on stack-up, layout, signal/power integrity.

• Familiar with guidelines for DO-178B, DO-254(2 DO-254 driven Designs) and FDA Medical Device Type II.
• 3 yrs (2012-2015)Medical Hematology cell counter(multi-physical: fluidics, RF, DC Field, Laser Scatter, motor interfaces: EMI, ESD mitigation) on multiple power supplies, A2Ds, D2As, CPLDs, FPGAs and mixed signal PCBs.
• 1 yr Powerline Adaptive Modem FPGA Design lead(6 FPGAs ~7.5 Million gates) and Simulation Verification lead.
• 1 yr Wireless Modem Logic Team Co-Design of next-gen 2 FPGAs + 2 mixed-signal ASICs.
• 10 yrs Disk Drive R/W Channel(Servo EMI) Co-Design on 5 mixed-signal ASICs. Some ASIC Physical Design.
• SW Design team algorithm lead(algorithm originator) on 2 novel disk drive CAD SW tools(ANSI C): (1) author of optimal short path search algorithm/derive 2-port passive element network transfer functions, (2) author of optimal search algorithm to predict state machine error propagation into disk drive readback data stream and (3) lead on SW optimization parameter update across multiple drive products, to optimize programmable parameters for both peak detect channels and head/arm gimble assembly servo control.

TECHNICAL SKILLS

• 8yrs ASIC, 10yrs FPGA, 2yrs Modem and 2yrs IFF Transponder Design.

10yrs digital scopes, spectrum analyzers, power supplies and signal generators. GPIB/IEEE488 programming. Schematic based design, some PCB layout and Signal Integrity SW. MS Visual Studio, Visual Basic UI, C, C++ and C# Lab Test coding projects of RF and Power Supply ATE equipment.

• 6 Embedded System Tools(includes 4 Integrated Development Environments) for Product Eval+Lab Debug:

ANSI C coding+debug of multi-threaded, multicore motherboards and embedded systems, on engineering r&d units and ate test rack equipment. TI Code Composer Studio, Altera NIOS II, Microchip MPLAB (IDE) Integrated Dev Env, HiTech-C, MCC18, ZENA Network Analyzer, PICDEM Z MRF24J40 2.4 GHz Motherboard and Daughter Cards, ATMEL AVR Studio 4.16, ATMEL ZigBEE Meshnetic Meshbean Development Board and WSNDemo S/W pkg.

•  Power PC(Freescale)/QUICC Embedded C debug using a DOS serial hyperterminal-type interface.
• Test Equip't For MIL-STD IFF Northrop Gruman Radio Comms: ATE Tower Test Rack Bringup Of IFF Radio Product. In Microchip IDE wrote and debugged Assembly Code, Embedded C and C, for 18F DSP and 33F DSP to control Radio Comms Test Equip't and Radio Power Supply Test. Serial Comms.
• Eng R&D Unit Test Of Flight Data Recorder(Aerospace FDR): Satellite Voice Over IP, Arinc429 Transceiver. VHDL and Verilog design of Altera FPGA with NIOSII processor. Signal Tap tool to store history of multiple internal interfaces. Serial interface (DB9) product legacy SW loads and NIOSII's C code compile and load into memory. Wrote minor C code in Quartus tool for the NIOS II processor.
• Eng R&D Unit Test Of Wearable Wireless Comms: Board component selection, schematic and light analog power supply design, light embedded C programs for GPS Subscriber handset, 2.4GHz 802.15.4 Wireless LAN, 1 SOC FPGA. Evaluated candidate IDE's wireless comms products for wearable product: writing and debugging Assembly code and C code with breakpoints, register writes/steps through, resume monitoring, etc..
• Eng R&D Unit Test Of Embraer Flight Air Management Control: TI128 DSP IDE to load/debug Assembly code and Compile C code to verify with breakpoints/stop/start. Wrote registers using IDE for onboard external device control such as: motor control writes/reads, sensors reads, motor control by current supply register writes, reads. Internal digital filter writes and reads and loop counter write/read for determinate task timing.
• Eng R&D Unit Test Of Arinc Airbus 380/Boeing 787 Radio Comms: Load an debug executable code into 386 Embedded processor via JTAG, to debug jetliner nose cone, HFDL Real Time, Global Long Range Arinc radio. Legacy WIN95 JTAG application, debug stop/start Assembly Code: HP Logic Analyzer 128pin data/address bus IO on-board Intel 86 Processor, for Rockwell Collins HFS-900D/CPL-920D.
• Multiple Board, FPGA, ASIC Tools: Altium 9.0, Xilinx Vivado, Synopsys VCS, Synopsys DC, Synopsys Prime Time, Orcad, Allegro, Cadence Verilog XL/NC VHDL, IBM theGuide and EinsTimer, MATLAB, Modelsim, ACTEL Libero 11.6, Debussy, Innoveda Viewlogic, MentorGraphics SPICE, Lattice ISP, Aldec8.1, Prep TBP(C,Verilog Transactors).
• Analog Conditioning Designs and FPGA Designs in multiple FPGA Families. Interfaced with multiple top-tier global ASIC Chip firms to do SPICE Model QA Simulations for corporate prepurchase due-diligence. Xilinx Vivado2018 for Ultrascale+ High Speed Serial Comms, MPSOC, Virtex7, Virtex5 QPRO, Spartan3A,Virtex2 and VirtexE FPGA families, Lattice FPGAs, Altera PLDs, NIOSII SOC Processor/FPGA, CycloneIII FPGA, CycloneIV and Cyclone V FPGA families.

ADDITIONAL SKILLS:

• Wrote many BASIC, Visual BASIC, FORTRAN, TURBO C and C++ SW programs for Test Equipment Control.
• Designed bench testers and test cards and wrote C++ software, Visual BASIC and EXCEL scripts to capture/analyze high-speed analog data, convert to MSPICE signal source format and control high-speed IEEE-488 interfaced test equipment (such as waveform synthesizers, logic analyzers and pattern generators) and optimize a PRML read/write channel(digital filter coefficients, DPLL gain, etc.).

• Consultant on purchases of an analog CAD network upgrade and high performance analog test equipment.
• Trained in HDL design, C++ and Digital Signal Processing

EMPLOYEE AWARDS/BONUSES:

2018  Exceeded Max %6.7 Annual Salary Merit Increase For Employee Performance  - Arthrex, Inc.
2013, 2014, 2015 Annual Employee Performance Bonuses(years: 2012, 2013, 2014) - Beckman Coulter, Inc.
2007 B1B Eng.Team Appreciation Award - Boeing Corp.. Most Valuable Engineer - ENEA Embedded Systems
2005 Kudos Award - Intel (Chipset Validation Multicore Platforms)
1988 Great Performer Award - Seagate Technology

EMPLOYER CHRONOLOGY: (some external contracts after 2006)

September 2020 to 2021 Current: FPGA Design For Aerospace Application. .

FPGA Contract=Aerospace Digital Circuit Design into Xilinx FPGA. VHDL Firmware Planning, UML

February 2020 to Covid19 SHUTDOWN March 2020-FPGA Designer(CONTRACTOR at Alif Semiconductor in Irvine, CA)

FPGA Contract=Convert ASIC Verilog and System Verilog into FPGA Design into Xilinx ZedBoard, Ultrascale+ RFSOC zcu111, Zynq MPSOC and Virtex vcu118 Eval Boards. RF Analog interface. High throughput data path with multiple interfaces including wireless, wired communications and multiple Embedded Processors with on-board Memory.

October 2018 to December 2019-FPGA Design Engineer (CONTRACTOR at Northrup Grumman in Southern California)

FPGA Contract1 at Mission Systems in San Diego, CA=Design High Speed Embedded C System VHDL FPGA in Xilinx Ultrascale+ MPSOC High Speed SerDes(Gigabit GTH XCVR), multi-processor device for Testing Multi-Board Aerospace Digital Comms w/Board level DDR4 and RFSwitch/Mux Control. Revision Control, TCL Scripts and State Machine waveform capture inside FPGA, with  multiple Xilinx Vivado 2018.x Integrated Logic Analyzers(ILA). FPGA Contract2 at Space1 Park in Manhattan Beach, CA=Re-packaged 2 legacy VHDL FPGA(s) in Xilinx ISE, with Serial Packet Comms/DMA in modern IO Boards to Test Multi-Board Space Digital Comms.

January 2017 - October 2018 Arthrex, Inc. Lab Test Engineer(PERMANENT)

Test Fixture Build and Implementation using: Embedded C, Python Quad Co.re Processor Programming For 16bit ADC, Logic Analyzer+Automated Averaged, USB Camera Image, FLIR Image Crop And OCR Text Mismatch, On-PC Board Component(s) Thermal Gradients, per RF Wand Output Loading. Hi-Voltage Switched Mode Power Supplies/Power Factor Correction, EMC, ESD, IEC 6061 compliance, Test Fixture Build And Test. MicroChip 18Fxxxx Controller, 3-Phase Motor Control BLDC, 3-Phase Hall Sensor, CPLD and FPGA VHDL code verification. 

November 2016 - January 2017 Qualcomm, Inc. FPGA Designer (CONTRACTOR)

Designed large scale Xilinx Virtex 7 FPGA with Embedded µProcessor, using Xilinx Vivado, High Speed Memory, AXI, I2C, I2S, SPI, USB serial interfaces. ASIC2FPGA conversion in a fast-paced, global team, aggressive schedule environment.

June 2016 - September 2016 Weidmann Technology, Inc. FPGA Designer (CONTRACTOR)

Altera Quartus Lite FPGA Design tool for: Embedded C Programming on Cyclone V SOC/FPGA Embedded Processor with Interface To External DSP. Lead custom RTL Design and Synthesis For FPGA High-Speed Front End ADC Interface (Designed In Verilog, Stable+Verified) plus External DDR2/3 High Speed Memory(Designed, Stable+Verified) and C based Data Traffic Generator DDR2 verification. Includes Interface to Signal Processing Computation Verilog Module.

• April 2016 – June 2016 (Best Buy - Florida) Sales Associate(PART-TIME)

Home Kitchen (major) Appliance Sales.

• May 2012 - Aug 2015 Beckman Coulter, Inc. In Miami-Kendall, FL Staff Electrical Engineer (PERMANENT)

FPGA/CPLD Design, Schematic based design,Light Board Analog, RF, Laser Scatter, Motor Sensors,
Solenoids. Freescale Power PC/QUICC Boot Debug, Serial Port Interface, NVRAM.
Cadence: Orcad, Allegro and PSPICE. Xilinx Spartan3A, Altera and Lattice FPGA and CPLD Designs
in both VHDL and Verilog. Light Analog and Board Design for EMI, ESD, EMC, IEC61000-4-3,
IEC 61000-4-2, multiple sensor and transducer interfaces for brushless motor
controls and sensors, fluidic flow controls, fluidic and laser module
temperature control, RF and Laser Light Scatter Detection. Freescale Power
PC Boot Debug, Serial Port Interface, NVRAM, SDRAM, Multiple PCBs.

BOM legacy obsolesence component analysis/industry search/compare and
procurement, component conversion, on-board test/debug and BOM update.

• February 2011-Jan 2012 Lockheed Martin In Orlando, FL. FPGA Electrical Engineer (CONTRACTOR)

Military(MIL) Aerospace requirements-driven FPGA design, Schematic based design.
Military Aerospace FPGA data processing design, in a requirements driven flow.
Xilinx Virtex5 QPRO, Xilinx ISE13.2, Cadence NC Verilog, Cadence SimVision,
Cadence Allegro, MentorGraphics DxDesigner.

• November 2009-November 2010 AAMSI Corp. In Fort Lauderdale, FL. FPGA Electrical Engineer (CONTRACTOR)

Schematic based debug, MIL Aerospace VHDL FPGAs, Aeroflex THOR Test Executive/TPS IRIS 2000
ATE Rack and board bringup for Northrop Grumman IFF Military Transponder, C and
Embedded C Coding. Programming RF Test Equip't For Avionics RF Comms(all
Programmable with Nat'l Instruments LabWindows CVI)/ Test Board/Adapter, ANSI C,
Embedded C, C#, Excel Visual BASIC, Programmable Environmental Test Equipment(Humidity,
Temperature,Vibration) For Mil Std 810F Certification.

• August 2009-November 2009 GE Aviation In Clearwater, FL. FPGA Electrical Engineer (CONTRACTOR)

Schematic based debug, MIL Aerospace 1 VHDL FPGA design for Video Graphics Buffer Controller
using ModelSim, Lattice Semiconductor 7.2, ISP Lever and Synplify per custom Video Data
Buffer algorithms.

• May 2009-August 2009 Avionica, Inc. In Miami, FL. FPGA Electrical Engineer (CONTRACTOR)

Schematic based debug, Aerospace Verilog Design of Satellite Voice Over IP, VHDL Verilog and
VHDL design of serial communication ports into aerospace Altera NIOSII SOC
Processor/FPGA, CycloneIII FPGA and CycloneIV FPGA families for Arinc 429,
Arinc 573, UART 232, PCM audio/voice, some light embedded C design and board
level lab debug with Digital Storage Scope, serial comms pattern generator,
10/100 Ethernet, PCI, 802.11 wireless comms.

• February 2009-April 2009 Isaac Daniel Group. In Miami, FL. FPGA Electrical Engineer (CONTRACTOR)

Board component selection, schematic and light analog power supply design,
light embedded C programs for GPS subscriber handset/wearable, 2.4GHz 802.15.4
Wireless LAN, 1 SOC FPGA. Power supply design, light firmware design for
handheld GPS Subscribed, 2.4GHz 802.15.4 Communication Network, using schematic
design tool ALTIUM v9.0(schematic design, analog simulation component
placement), Xilinx ISE 10.1 for Coolrunner CPLDs, Coolrunner Evaluation Board
and microcontroller/wireless development tools: Microchip MPLAB (IDE).
ZENA Network Analyzer, PICDEM Z MRF24J40 2.4 GHz Motherboard/Daughter Cards,
ATMEL AVR Studio 4.16, ATMEL ZigBEE Meshnetic Meshbean Development Board and
WSNDemo software package

• November 2008-February 2009 Technisource In Fort Lauderdale, FL. FPGA Electrical Engineer (CONTRACTOR)

Aerospace VHDL code inspect/simulation for Hamilton Sundstrand Overspeed
Fuel Controller aerospace ACTEL FPGA. ARINC 429 test script inspection.
Code extraction and simulation per required test steps and pass/fail
requirements of VHDL source code for Hamilton Sundstrand Overspeed Fuel
Controller aerospace ACTEL FPGA. Simulate with ACTEL Libero v8.4 Modelsim.
ARINC 429 test script inspection per extracted pass/fail requirements.

• May 2008-October 2008 IBM in Rahleigh, NC. FPGA Electrical Engineer(CONTRACTOR)

IBM Embedded Power PC. Team design of 45nm, 1GHz Digital ASIC and 1 Xilinx
FPGA with internal Embedded PowerPC. IBM EDA tools theGuide, EinsTimer, Verilog
HDL for logic design, synthesis and timing closure at 45nm channel length, >1GHz
multiple clock domains. Tcl, perl, kde, unix, and AIX scripting.

• February 2008-April 2008 GE Aviation in Rockford, IL. FPGA Electrical Engineer (CONTRACTOR)

EMBRAER jet cabin rig, Schematic based debug, Embedded C debug/light coding TI128 DSP
to debug air management analog control. Participate in team review of Embedded Software control of
position/temperature/pressure sensors, valves and motors.

DO178-based, requirements driven debug of embedded C software. Lab verification using a
cabin mockup lab for a commercial jet cabin closed loop airflow
controller card with current-controlled motor drivers and analog position,
pressure and temperature sensor feedback to Embedded SW. DOORS on doc views,
TI Code Composer IDE for TI 2812DSP debug and LABVIEW.

• January 2007-December 2007 Boeing in Long Beach, CA. FPGA Electrical Engineer (CONTRACTOR)

DO254, 2 MIL FPGAs for Network Centric Future Combat Systems.
DO254 VHDL design into Xilinx FPGAs using Xilinx ISE, Mentor ModelSim and
some board level analog sensor interface design(ex. low pass active filters
for sampling ADC, etc.) with Cadence(PSPICE, Allegro, etc.). From DOORS
requirements, contribute top level architecture definition and memory maps
to embedded system design using IBM Power PC core plus peripherals.
Schematic based design.

Familiar with Xilinx embedded system design tool SDK-EDK(includes Xilinx's
Embedded Processor Studio). ACTEL FPGA programming and MIL STD 1553 interface.
LabView PCI I/O card.

• September 2006-December 2006 Rockwell Collins in Melbourne, FL. FPGA Electrical Engineer (CONTRACTOR)

1 FPGA, 1 CPLD, Arinc 429, 386 Embedded C, JTAG, Software Defined Radio(HFDL Real Time,
Global Long Range) Embedded HFS-900D/CPL-920D: (ARINC 753/635), ARINC 719, ARINC 429-compatible,
DO-160C-compliant, DO-178 Level C-compliant, ARINC 615 data-loadable, OMS BITE.
Boeing/Airbus. VHDL design into Altera PLDs, using Mentor ModelSim 6.1, Altera Quartus2,
Actel A42MX24-PQ-160I FPGA, HyperLynx and PADs, Some assembly code/real time code debug, board debug for
Boeing 787 and Airbus A380 ARINC radio comms and JTAG. Schematic based debug.

• January 2006-September 2006 Raytheon in Towson, MD. FPGA Electrical Engineer (CONTRACTOR)

DO254, UML, 1 MIL FPGA and S/W for Network Centric Future Combat Systems.
DO254 VHDL design from DOORS requirements into Spartan3(million gate+) FPGAs
for board level RF-based products, using Mentor ModelSim 6.1, Synplify,
Xilinx 7.1i and UML(Universal Modeling Language) for radio communication
equipment, Transponders, KIV-77. Completed project 5 months early to meet
an accelerated schedule. Schematic based design.

• 2005-2006 Intel Corporation in Chandler, AZ. Component Engineer. (PERMANENT)

Multi-Core Single Board Computer Embedded C/Linux/Perl code for Debug Scripts.
ASIC/FPGA CPLD and high-speed, multi-core IA-32 platform board verification in
lab. Used QUICKTURN and Intel’s In Target Probe(ITP) for REMOTE boot loader and
FPGA Verilog/VHDL emulation verification, Perl, C, Linux scripting and
in-house custom verification tools to verify complex, large scale chipsets
and motherboards, writing additional and/or improving existing custom SW
tools. Schematic based debug.

• 2002-2003 Adaptivenetworks Incorporated in Newton, MA. Senior Logic Designer (PERMANENT)

6 FPGAs for Adaptive Powerline Modem. ~7.5Million logic gates for 512pt FFT/IFFT,
Fixed/Floating Point, IIR/FIR Digital Filters, Multiple Clock Domain, 130MHz. Schematic based design.

• 2001-2002 Tantivy Corporation(Harris Corp. spinoff) in Melbourne, FL. Senior Logic Designer (PERMANENT)

2 FPGA and 2 ASIC Designs with TI59xxx MCU and Power PC interfaces, FIR/IIR Filters
And Turbo Coding for Next Gen GHz RF, I95-CDMA Wireless Cell Phone Transceivers. Schematic based design.

• 1996-2001 SmartDisk Corporation. in Naples, FL FPGA Logic Designer (PERMANENT)


7 FPGA and 7 ASIC Designs for Crx16 Coin Size Battery-Powered Solid State Data Storage
Devices with interfaces to ATMEL AVR and FPGA Embedded 32Bit ARM processors. Schematic based design.

• 1987-1996 Seagate Technology Incorporated in Minneapolis, MN. Advisory Electrical Engineer (PERMANENT)

5 Mixed Signal, 80MHz to 350MHz ASIC Designs with PRML, Convolutional Coding for High
Capacity/High Speed Disk Drive Data Storage. Differential PECL and precision analog buffers and
differential analog filters on-board. HPBASIC, IEE488, GPIB programmable Test Equipment and
with DOS, Visual BASIC and C++ for automated test equipment control and graphing test data. Schematic based design.

ADDITIONAL WORK HISTORY:

Engineering Aid
1984-1986 Naval Ocean Systems Center in Point Loma, California
Electronics Systems(Secret Clearance from 1984 to1986)

Teacher Assistant(TA)
1986 Summer Session at UCSD in La Jolla, California
3rd year level Analog Electronics course(Prof. Hugh Chivers lectured 3 hours
a week and wrote exams-2 TA's taught problem solving classes, taught and
ran labs and graded homework, labs and exams)

EDUCATION

UNIVERSITY OF CALIFORNIA AT SAN DIEGO in La Jolla, California
B.S. Electrical Engineering And Computer Science/Electronics Systems June 1986
PROVOST's HONORS LIST

EMPLOYEE AWARDS/BONUSES:

2013, 2014, 2015 Annual Employee Performance Bonuses(years: 2012, 2013, 2014)- Beckman Coulter, Inc.
2007 B1B Eng.Team Appreciation Award - Boeing Corp.. Most Valuable Engineer ENEA Embedded Systems
2005 Kudos Award - Intel (Chipset Validation Multicore Platforms)
1988 Great Performer Award - Seagate Technology

CERTIFICATIONS

1999 UCLA Extension Short Course. Design For Test
2000 UCLA Extension Short Course. Digital Signal Processing
2000 UCLA Extension Short Course. Error Control Coding
2005 Intel Corporation Short Course. Linux Remote Workstation Debug Environment

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example 1. A 'GENERIC, REQUIREMENTS BASED EMBEDDED uP FPGA DESIGN TEAM FLOW

[CREATE FPGA REQUIREMENTS AS 'ALL PAPER' REQTs DESIGN+REQTs TEAM REVIEW/ACCEPTANCE] 
Reqts Capture Tool, Marketing Reqts, Team Discussions, Vendor Management(Quality Flow, Processes), Legacy+New Component Data Sheets, Applicable Standards Contribute Reqts, Quality Flows, Work Flow Personnel, Design/Verification Tools+Processes, Legacy Lab Tests+Feasibility Lab Tests Capture More Reqts. Risk Planning(Ex. New IP, tools, vendors, materials etc.). Team Review Of Reqts And Acceptance. 
[per Reqts: PROCURE S/W+H/W DEVELOPMENT TOOLS TEST EQUIP'T, DEMO BOARD(s)]
[per Reqts:DESIGN FPGA+SIMULATION TESTBENCH CODE+EMBEDDED uP C S/W FOR DEMO BOARD(s)]
Custom VHDL/Verilog and C Code.
[per Reqts: DEVELOPMENT LAB TESTS AT EARLIEST/IN PARALLEL WITH DESIGN]
Prototype Test C Code S/W on FPGA Embedded µProc. to control FPGA (VHDL/Verilog) modules.

example 2. DEVELOPMENT LAB TEST FPGA PROTOTYPE  EMBEDDED uP C CODE S/W+CUSTOM  (VHDL/VERILOG)

1. Simulate: Demo Board FPGA(custom VHDL/Verilog) modules, (prior to, parallel with) Lab Tests.
2. Lab Test FPGA(FPGA Embedded µP(C code S/W)+custom VHDL/Verilog):

• Embedded µP S/W configures FPGA Modules(VHDL/Verilog).for preprocess+storage
• Embedded µP S/W triggers fast capture(ex. A2D'd baseband BPSK)+preprocess+storage
• Embedded µP S/W triggers fast DMA data xfer to External DDRx(at 100's of MHz).
• Embedded µP S/W reads in DDRx data for FPGA verify+postprocess(option to Host Display Verify).

[... and so forth, per Reqts ..]

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